1. Field of the Invention
The present invention relates to a method of and an apparatus for transferring data between circuits. In particular, the present invention relates to a technique of reducing a transfer delay time so as to transfer data asynchronously at high speed between circuits that operate at different clock frequencies in an LSI chip or in different chips.
2. Related Art
FIG. 1 shows data transfer between two circuits A and B that operate independently of each other on clock signals Clock_A and Clock_B, respectively. These clock signals oscillate at different frequencies, for example in 20FIG. 1, the clock signal Clock_A at a higher frequency and the clock signal Clock_B at a lower frequency. The data transfer is usually achieved by a handshake technique or an asynchronous RAM technique. These techniques will be explained.
(1) Handshake Technique
FIG. 2 roughly shows handshake data transfer between the circuits A and B, and FIG. 3 is a timing chart showing the handshake data transfer. In FIG. 2, each part encircled with a dotted line includes two flip-flops to settle a meta-stable state, which is a transient oscillating state caused when receiving a signal. The two flip-flops delay data transfer timing by two pulses, and therefore, the circuits A and B start each the next operation in response to the second pulse after the reception of a signal.
A handshake data transfer operation from the circuit A to the circuit B will be explained. The circuit A sends a signal TransferStart to inform the circuit B of the start of data transfer. The signal TransferStart is delayed by two pulses and forms a signal TransferStart_To_B, in response to which the circuit B recognizes the data transfer from the circuit A. The circuit B returns an acknowledge signal TransferAck to the circuit A. The signal TransferAck is delayed by two pulses and forms a signal TransferAck_To_A, in response to which the circuit A recognizes that the circuit B has received the data. The circuit A negates the signal TransferStart to inform the circuit B of the completion of the data transfer. The negation of the signal TransferStart is delayed by two pulses and negates the signal TransferStart_To_B. In response to this, the circuit B recognizes that the signal TransferStart has been negated and negates the signal TransferAck. The negation of the signal TransferAck is delayed by two pulses and negates the signal TransferAck_To_A. In response to this, the circuit A recognizes that the signal TransferAck has been negated. This completes the handshake data transfer operation.
(2) Asynchronous RAM Technique
FIG. 4 roughly shows asynchronous RAM data transfer between the circuits A and B. This technique arranges an asynchronous RAM 1 between the circuits A and B. The RAM 1 has a data write port, a data read port, an address write port, and an address read port. The circuits A and B independently carry out write and read operations according to the respective clock signals Clock_A and Clock_B of different frequencies. The RAM 1 absorbs the frequency difference between these clock signals.
The related arts (1) and (2) mentioned above have some problems. The handshake technique (1) makes the both circuits A and B acknowledge every reception of a control signal such as TransferStart or TransferAck when transferring data between the circuits A and B. Accordingly, the handshake technique needs a long time to transfer each piece of data. As shown in FIG. 3, a transfer delay time tTD involved in transferring a piece of data from the circuit A to the circuit B by the handshake technique is very long. Namely, the handshake technique needs a large overhead time that is irrelevant to data transfer itself and is wasted for handling a variety of control operations. The handshake technique processes each transfer request sequentially, and transferring xe2x80x9cnxe2x80x9d pieces of data by the handshake technique will expand the delay time tTD by xe2x80x9cnxe2x80x9d times. In this way, the handshake technique involves a long transfer delay time, and therefore, is not appropriate for transferring a large amount of data.
On the other hand, the asynchronous RAM technique (2) must arrange an asynchronous RAM for each transfer direction. More precisely, the one-way data transfer of FIG. 4 needs an asynchronous RAM having two data ports and two address ports. But to carry out two-way data transfer, two asynchronous RAMs each having two data ports and two address ports are needed. In this way, the asynchronous RAM technique involves a large increase in the quantity of hardware.
This invention is intended to overcome the above mentioned problems. An object of the present invention is to provide a method of and an apparatus for achieving two-way asynchronous data transfer between circuits operating at different clock frequencies, capable of reducing data transfer overhead, so as to shorten a transfer delay time, and transferring data at high speed without greatly increasing the quantity of hardware.
In order to accomplish the objects, the present invention generates a reference signal from two clock signals of different clock frequencies that drive two circuits between which data is transferred. One of the circuits serving as a source circuit uses the reference signal to instantaneously recognize the completion of data transfer inside the source circuit. FIG. 5 shows an example of a apparatus and method for realizing the present invention.
The present invention provides an apparatus of FIG. 5 for transferring data between a source circuit 2 and a destination circuit 3. The circuits 2 and 3 operate independently of each other at different clock frequencies. Namely, the circuit 2 operates on a first clock signal having a first frequency, and the circuit 3 operates on a second clock signal having a second frequency that is lower than the first frequency. The apparatus has a reference signal generator 13 for generating a data transfer reference signal, which involves a pulse that is within a cycle of the second clock signal and is synchronized with a pulse of the first clock signal.
The source circuit 2 uses the reference signal to determine whether or not the destination circuit 3 has completely received data transferred from the source circuit 2.
Each reference signal always involves a pulse that is within a period of the second clock signal, so that the destination circuit 3 operating on the second clock signal surely receives data from the source circuit 2. The reference signal allows the source circuit 2 to recognize the completion of data transfer from the source circuit 2 to the destination circuit 3 without an acknowledge signal from the destination circuit 3. This reduces data transfer overhead and shortens a transfer delay time.
The data transfer reference signal may be generated by a circuit of FIG. 6. This circuit comprises a first flip-flop circuit 22 that receives a signal whose frequency is half the second frequency and operates on the second clock signal, second flip-flop circuits 23, 24, and 25 that are connected to the first flip-flop circuit 22 in series and operate on the first clock signal, and an EXOR (Exclusive OR) circuit 26 for providing an EXOR of two output signals having different phases from the first and second flip-flop circuits.
Alternatively, the data transfer reference signal may be generated by a circuit of FIG. 8. This circuit comprises a first flip-flop circuit 22 that receives a loop-backed signal of a NAND of a signal generated by the reference signal generator and operates on the second clock signal, second flip-flop circuits 23, 24, and 25 that are connected to the first flip-flop circuit 22 in series and operate on the first clock signal, and an EXOR circuit 26 that provides an EXOR of two output signals having different phases from the first and second flip-flop circuits.
If the operating clock frequencies of the two circuits are close to each other, the present invention inserts a third circuit 4 of FIG. 13 between the two circuits 2 and 3. The third circuit 4 operates on a clock signal whose frequency is higher than those of the first and second clock signals. The third circuit 4 relays data between the circuits 2 and 3 so that the third circuit 4 realize the data transfer mentioned above.
In other words, the configuration involving the third circuit 4 is capable to generate the data transfer reference signal and shorten the transfer delay time even if the operating clock frequencies of the source and destination circuits are close to each other.
To carry out reverse data transfer from the circuit 3 operating at the lower frequency toward the circuit 2 operating at the higher frequency with a transfer request from the circuit 3, the present invention may arrange read buffer circuits (41, 42) of FIG. 12 for the circuit 2. The read buffer circuits (41, 42) hold data transferred from the circuit 3. The read buffer circuits eliminate the need of transmitting a transfer request for each piece of data. This shortens a transfer delay time when continuously transferring data.
Other and further objects and feature s of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.